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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">CTICONTROL, CTI Control register</h1><p>The CTICONTROL characteristics are:</p><h2>Purpose</h2>
        <p>Controls whether the CTI is enabled.</p>
      <h2>Configuration</h2><p>CTICONTROL is in the Debug power domain.
    </p><h2>Attributes</h2>
        <p>CTICONTROL is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="31"><a href="#fieldset_0-31_1">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">GLBEN</a></td></tr></tbody></table><h4 id="fieldset_0-31_1">Bits [31:1]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-0_0">GLBEN, bit [0]</h4><div class="field">
      <p>Enables or disables the CTI mapping functions. Possible values of this field are:</p>
    <table class="valuetable"><tr><th>GLBEN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>CTI mapping functions and application trigger disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>CTI mapping functions and application trigger enabled.</p>
        </td></tr></table><p>When GLBEN is 0, the input channel to output trigger, input trigger to output channel, and application trigger functions are disabled and do not signal new events on either output triggers or output channels. If a previously asserted output trigger has not been acknowledged, it is <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span> which of the following occurs:</p>
<ul>
<li>The output trigger remains asserted after the mapping functions are disabled.
</li><li>The output trigger is deasserted after the mapping functions are disabled.
</li></ul>
<p>All output triggers are disabled by CTI reset.</p>
<p>If the ECT supports multicycle channel events any existing output channel events will be terminated.</p><p>The reset behavior of this field is:</p><ul><li>On an External debug reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h2>Accessing CTICONTROL</h2><h4>CTICONTROL can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>CTI</td><td><span class="hexnumber">0x000</span></td><td>CTICONTROL</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When SoftwareLockStatus(), accesses to this register are <span class="access_level">RO</span>.
          </li><li>When !SoftwareLockStatus(), accesses to this register are <span class="access_level">RW</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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